Processed semiconductor wafers typically comprise an array of substantially isolated integrated circuitry which are individually referred to as "dies". The "dies" are also commonly referred to as "chips" and comprise the finished circuitry components of, for example, processors and memory circuits. One common type of memory circuitry comprises DRAM chips.
Not all chips provided on a semiconductor wafer prove operable, resulting in a less than 100% yield. Accordingly, individual dies must be tested for functionality. The typical test procedure for DRAM circuitry is to first etch the upper protective passivation layer to expose desired bonding pads on the individual dies. Thereafter, the wafer is subjected to test probing whereby the individual dies are tested for satisfactory operation. Inoperable dies are typically identified by an ink mark. The wafer is severed between the individual dies, and the operable, non-marked dies are collected.
The "operable" individual dies are then assembled in final packages of either ceramic or plastic. After packaging, the dies are loaded into burn-in boards which comprise printed circuit boards having individual sockets connected in parallel. The burn-in boards are then put into a burn-in oven and the parts are subjected to burn-in testing. Thereafter, the dies are re-tested for operability. In other words, the dies are subjected to a test after severing and packaging, and have an individual opportunity to fail. Note that such requires two separate tests.
U.S. Pat. No. 5,047,711 to Smith et al. discloses a technique whereby individual circuits are subjected to burn-in testing while still constituting a part of a yet to be severed wafer. It would be desirable to improve upon these and other techniques for fabricating wafers and testing individual dies prior to their severing from the semiconductor wafer.